The Department of Electronics and Communication Engineering organized a six-day hands-on training program on “System Verilog Verification and Analog IC Design” from 18–23 August 2025. The workshop was conducted by Mr. B. Arivazhagan and Mr. S. Vasantharajan, Design Verification Engineers, eDigiM Research Pvt. Ltd., Chennai. A total of 80 students participated in the program.
The training provided practical exposure to System Verilog-based digital verification, Analog IC design, mixed-signal simulation, and VLSI design methodologies, helping students enhance their industry-relevant skills in semiconductor and hardware design technologies.